Electronic design, or at least digital design, is a branch of applied logic.

In fact, in England a digital designer is called a: ‘logician.’ Increasingly, all electronic design is digital design. Part of this is due to Moore’s law about scaling (the number of transistors per unit area on a Silicon Wafer doubles every 1.5 to 2 years *). The other part has to due with determinism and modeling.

To clarify, it is only digital designs that scale according to Moore’s law and, further, only digital designs can be modeled deterministically. Analog, the alternative to digital, relies on actual currents and voltages as opposed to ‘logic states.’ Currents and voltages are often dependent on IC parameters that do not ‘scale well’ (easy to shrink). Further, analog circuits are modeled with such programs as all (>1000) the various flavors of SPICE. The standard versions of SPICE rely on Nodal Analysis which happens to be computationally intractable. [For digital circuits, dedicated simulators exist that run orders of magnitude faster than the traditional SPICE tools.]

Back in the heroic age of electronic and µP ( microProcessor ) design (mid-to-late 1970s), EDN (or equivalent - perhaps Electronics or Electronic Design) used to publish tests (not online - before the rise of the Internet) about electronic/electrical savvy. If you scored below a certain score you were labeled, with opprobrium, as a ‘programmer.’

Well, now, all most all electronic designers are ‘programmers’ - VHDL and (our personal preference) Verilog have seen to that. Both are HDLs - Hardware Definition Languages. Also, as I remember it, right above ‘programmer’ was ‘TTL Jockey’ - these days I suppose that would be: CMOS Jockey.

My own personal background was Mathematics and Logic (and Analytic Philosophy) - not an electron to be seen anywhere. However, programming is even more obviously applied logic. Think Turing and Church: Turing Machines, Church’s Lambda Calculus.

In fact, after I finished my MA in Computer Science I had to rely on such aids as the ACM’s review article about the relationship between logic and transistors to get me over the hump (when I relocate my copy of it I will scan it and publish it online). In fact some of us used to joke about getting radiation burns if we got too close to the hardware.

Computer Architecture and Logic Architecture

Both Computer Architecture and Logic Architecture are meta Digital Design. Since digital design comprises more than computer design but all computer design concerns logic then Logic Architecture may be considered the more general term.

Motivation

But the first real real-world problem that I tackled was the problem of video compression and understanding. Starting in the mid 70s I became intrigued with (and had reasons to solve problems in) methods of video compression and understanding. I saw them as linked problems. I also understood them to be inherently hierarchical problems.

To start with a low-level example, I immediately realized (ca 1974 - while in grad school) that video compression would be greatly improved by using key-frames (that is not what I called them but that is what they are now known as) and then recording the differences from that frame. But I took that a step further and realized that you might be able to improve on that by having a hierarchy of key frames - especially with a fixed camera as in security (to this day no one except me has implemented this).

But to implement a hierarchy of key frames you really need an alternative method of image description - to whit image understanding (IU).

A panalopy of imagers (POM)

But IU is extremely difficult to achieve with a single imager. As an example, let us consider what a hierarchial description of a static scene might look like:

Realistically, such a description requires more than one imager imaging the scene. 3D structures are far easier to derive with a multipe-point-of-view (MPOV) camera system. Two points of view (POVs) might be sufficient but most consider three to be the bare minimum. But I would go much further and suggest the more the merrier. In fact I would urge a panalopy of imagers (POM) with many different types of imagers with many different lenses and many different vergences; but all coherently aimed at a single scene.

One reason to take this approach is that imagers and adequate lenses are becoming incredibly cheap. At the moment (Q4 2006), Micron has extremely high performance imagers at bargain prices (<$10) that require no (well almost no) support circuitry. Adequate lenses are also available for under $10. High-quality, board-level cameras can be built for ~ $20.

However, to continue the general discussion, let us consider a quasi static scene. Using an MPOV camera system you can derive a 3D structure for the scene - and also a texture map. If you have the luxury of full system "training" you can also train your system under a continuum of lighting conditions. And with an MPOV system you should be able to distinguish shadows from other features - shadows have no 3D structure. So a hierarchial description could include the underlying 3D structures that are constant in the scene plus illumination models. When actors enter the scene they can be readily (we can always hope) extracted and analysed independent of the static scene. In an MPOV system that analysis can also be 3D + texture + motion. And so on.

There are a great many other compelling reasons to go down this particular road that I have been investigating, off and on for 30+ years, but they are only available from me as a white paper under NDA. For additional thoughts about MPOV systems etc. see a discussion at the holographic camera system site (holocam.com).

But, to continue on the theme of a "life in logic," in the process of developing imaging systems I have needed to do a great deal of system/logic/computer architecture - and at a lower level: digital design.

Additional Logic Architectures and Digital Designs with Comments (Firsts and Almost Firsts):

Event counters for asynchronous processor signaling:

We were developing a dual processor (6502/6512 running on opposite clocks) system and we wanted a reliable, deterministic signaling method that would not force either µP to wait (halt). Basically, I adapted to asynchronous process signaling a method that I use (from Knuth, Fundamental Algorithms) for handling barrels and barrel pointers. Later I found that someone had already described the method in the ACM (event counters) at about the same time that we implemented it in our system.

First IBM Channel I/F realized with an 8-bit MOS processor:

We wanted to use a 6502 but our client forced us to use an Intel 8085A. We needed a tremendous amount of ingenuity to accomplish this task: including first use of a LUT to look-up the channel commands and I/O addresses. Note that it would have required just as much ingenuity with the 6502 as well, but the design would have been much cleaner.

Arbitrary waveform generators and direct digital synthesizers ARB/DDS:

In the 1980s we were designing/developing novel linear and non-linear warpers. Both types had integral z-buffers and one of the non-linear warpers was able to invert a rational bi-cubic transform. One day I realized that I could adapt (by the addition of a sine look-up table [LUT]) these warpers to arbitrary tone generation. And that the tones so generated could be in arbitrary phase relationship to each other, which solved a (then) current problem in digital tone generation. Just as I was about to file a patent on this technology I saw the first announcement of a DDS.

Crash-and-burn, thermometer-code-based rate adaption:

I really regret not patenting this one because Analog devices came out with this about five years after we had built one in the lab. I conceived it as the all-digital equivalent of rate adaption via an ADC followed by a DAC – the then current crash and burn method. The thermometer code serves as an analogue to the analog signal.

Novel, systolic-processing-enhanced CCP – the twist CCP:

A variety of vendors offer custom-computing (CC) platforms (CCP) based on FPGAs. The platform is usually a PCI card with several interconnected FPGAs plus additional resources, most typically memory. Some, such as GigaOps, took the architecturally interesting approach of having a PCI baseboard on which you could stack their (stackable) FPGA modules. I designed a similar FPGA based CCP with a slight twist. As you stacked each module you rotated it 90 deg CW relative to the one below. I added this architectural flourish in order to better accommodate systolic processing architectures. However, I decided not to commercialize our twist CCP because of the large number of CCPs that were already on the market.

*The original statement in the 1965 Electronics article was that the doubling would occur every year. Ten years later Moore hedged that to every two years. It is now often quoted as every 18 months.