The two basic components of an ARB/DDS are the phase accumulator and the phase-to-magnitude converter.
For purposes of the discussion below, assume that the design is being realized inside of an FPGA [e.g., Actel proAsic 3, Altera Cyclone III, Xilinx Spartan 6, et cetera].
The phase accumulator consists of an adder with an output register, an input phase-increment register, and a data path back from the output register to the "other input" of the adder [the accumulator data path].
The phase to magnitude to converter is usually constructed from a LUT. The input address is the output of phase accumulator's output register. The output of this LUT can then be shipped off to a DAC for the actual tone generation.
In the case of a DDS, the LUT can be read-only with values for a sine wave. For an ARB, the LUT should be re-loadable.
The ratio between the input clock to the accumulator and the signal to be synthesized needs to be high for output signal accuracy. In other words, you do not want to traverse the entire LUT in just several clocks. Equivalently, the phase increment should be as small as possible. One indication of signal accuracy is output jitter. If you have excessive output jitter than your phase increment is [probably] too high.
Ultimately, output signal accuracy and output jitter are ameliorated in the low-pass filter at the DAC output. Just don't expect too much from the LPF.
A typical design example for synthesis of relatively low frequency tones with a high-frequency phase accumulator clock would be as follows:
- A 24-bit accumulator
- feeding a 1024 word LUT
- each word 10-bits [or if inside an FPGA - whatever is handiest*].
Since, in this example, the LUT has only 10 address bits, only the most significant 10 bits of the accumulator data path are mapped to it. The phase accumulator data format is, therefore, of the form: [10b14]
There is an interesting subcase of this in which you wish to use a DDS to generate a square wave. Obviously, the MSB out of the phase accumulator register can give a square wave of the appropriate frequency; but with what accuracy? As with the sine wave case the accuracy is a function of the phase accumulator clock and the actual value of the phase increment - the lower the value the greater the accuracy. [We realize that the value for the phase increment is a function of: the phase-accumulator clock, and the number of bits in the accumulator. The actual function is left as an exercise to the reader.]
NOTE: Bringing out the MSB of the phase accumulator to a pin is worthwhile to consider - since it will give you an immediate and direct way of measuring the jitter of your DDS.
With this square-wave case you might want to look to other methods for cleaning up the output than the DAC and LPF. The two figures of merit for this square wave case reduce to:
- duty cycle
- jitter.
The obvious method, of running the circuit twice as fast and then taking your square wave into a divide-by-two circuit, will not yield any benefit here since any deviation from a 50% duty cycle is solely due to jitter; and you have done nothing to improve jitter.
Which leads us to the conclusion that the only thing that we need to worry about is jitter.
But how to solve this without the DAC and the LPF? Or can you? First of all, to have any hope of solving this problem by digital filtering - you will need to be able to clock the filtering circuits faster than the phase accumulator [at least that is our current thinking].
Several lines of attack:
- Run two or more DDSs with slightly different initializations, s.t., you know that the actual MSB transition will always occur somewhere between DDS1 going true and DDS2 going true and in a very narrow window.
- Use the LUT, but no need for a sine output - the LUT would be loaded with all ones or all zeros except around the transition point. And just use several bits of precision - no need for 8 or more bits of precision - additional bits are only needed for waveform accuracy and do nothing for zero crossing accuracy for a square wave.
- Emulate the reduced-accuracy-DAC function inside the FPGA.
- Use any of the above with some simple external low-pass filtering [but no DACS].
More later. Any questions, comments or suggestions on this topic jitter?
*In a Xilinx Spartan 6 the LUT would probably be configured as: 2K x 9-bits. In the Altera Cyclone III and the Actel proAsic3 as: 512 x 9.
