Image Processing Tile (IPT) With Camera And Stepper Support

System Summary

We designed the IPT as a processing tile with image processing capability. Its additional capabilities include imager control, imager data capture, stepper control, communications and man-machine I/F. The raw processing power comes from two Xilinx FPGAs (up to 2 million gates equivalent each) and two Analog Devices ADSP-TS201S TigerSHARCs (3.5 GFLOPS each). An ARM 920T core processor (Cirrus Logic EP9312/15) capable of running microLinux provides overall system control with communications and man-machine I/F.

All imager control and data communication, and inter-tile communication will be realized with the ultra high-speed LVDS capabilities native to the Xilinx FPGAs. Only if we are interfacing to an already existing imager module that lacks LVDS or equivalent (the Xilinx FPGAs support four flavors of LVDS plus two differential signal standards similar to LVDS) will we not use LVDS or equivalent.

Philosophy of Design

Many image-processing operations are inherently neighborhood operations and are best accomplished with ASICs or their FPGA analogues. [resources: row buffers, data-path resources with associated ALUs including single cycle multiplier-accumulators (MAC)]. Yes, if you need to visit every pixel, DSPs just don't hack it - you need an ASIC or its FPGA equivalent.

Goals

The IPT has the capability to support such projects as HoloCam’s own MPOV camera system, Dr. Narendra Ahuja’s omnifocal panoramic camera system, various hybrid video-laser data acquisition systems, and any other compute intensive image processing tasks that require high-performance imager support. We are designing it as a tile in order to support multi-imager systems and such very computationally demanding image processing tasks as:

Capabilities

Modular Development

Obviously, the fact that the sub-modules are amenable to independent development allows us to partition the development task. For instance, the first two parts might make excellent Beckman Institute projects with the first one well within the capacity of seniors at UI and the second within the capacity of grad students.

Flexibility

Two of the three modules are software driven and the third is SRAM FPGA based. As long as we take some care in our design it should remain an extremely powerful, state-of-the art, general purpose, flexible image processing system for a long time to come. This design flexibility yields flexibility in changing the target imagers and applications. It is also insurance against obsolescence: each sub-module can be updated independently of the others as more powerful devices become available without changing application code. In the case of the FPGAs, actual bitstreams might change (device retargeting) but the actual internal FPGA design (schematics and HDL) will remain the same unless additional external or internal changes are made to the design.

Horsepower

As mentioned above, raw processing power comes from two Xilinx FPGAs (up to 2 million gates equivalent each) and two Analog Devices ADSP-TS201S TigerSHARCs (3.5 GFLOPS each). Even the Cirrus Logic EP9312/15 based on the 32-bit ARM 920T core is capable of eight MIPS and contains a floating point DSP coprocessor. Additionally, the EP9312/15 contains an MMU for Linux and Windows CE support: